//+FHDR-------------------------------------------------------------------------
//            __     __ __                  ____     ___ ___
//           |  |   |  /__| ____ ___ ___   /    \   /  ____/
//           |  \___/  |  /   __    __   \/  __  \ /  /
//           |   ___   |  |  /  \  /  \     /__\  (  <
//           |  /   \  |  |  |  |  |  |    /    \     \____
//           |__|   |__ __ __|  |__|  |___/      \__ __ ___\ 2.0                     
//------------------------------------------------------------------------------
//-- Module Name     :    fp_input_path_switch
//-- Hierarchy       :    frame_process - * - fp_input_path_switch
//-- Description     :    Interface                                             
//                                                                              
//-- Last Modified   : 2013-01-29 20:00
//-- Revision history:                                                          
//     Date               Author       Description                              
//     2012-12-25 20:32   Tiger          Initialize code
//-FHDR-------------------------------------------------------------------------

`timescale 1ns/100ps

/***************************************************************/
//     输入时在插入和MAC/拆帧接口间选择通路的选择器模块
//     优先插入模块。
/***************************************************************/
//插入模块的接口好像没有用
module fp_input_path_switch(
                            input wire clk,
                            input wire rst_n,

                            //与rx_ctrl接口
                            input wire rx_rdy,
                            output wire rx_ff_sop,
                            output wire rx_ff_eop,
                            output wire rx_ff_dval,
                            output wire rx_ff_dsav,
                            output wire [255:0] rx_ff_data,
                            output wire [4:0] rx_ff_mod,
                          //  output wire rx_ff_err,                                   //*
                            output wire [7:0]src_node_id_i,
                            output wire is_insert_frame,
                            output wire [7:0] insert_des_node_id,
                            output wire[2:0] pri_insert_o,
    
                            //与mac或拆帧模块接口
                            output  reg rx_rdy_mac,
                            input wire rx_ff_sop_mac,
                            input wire rx_ff_eop_mac,                                
                            input wire rx_ff_dval_mac,                               
                            input wire rx_ff_dsav_mac,
                            input wire [255:0] rx_ff_data_mac,
                            input wire [4:0] rx_ff_mod_mac,
                          //  input wire rx_ff_err_mac,                                //*
                            input wire [7:0] src_node_id_i_mac,

                            //与插入模块接口
                            output wire rx_rdy_insert,                               
                            input wire rx_ff_sop_insert,
                            input wire rx_ff_eop_insert,
                            input wire rx_ff_dval_insert,
                            input wire rx_ff_dsav_insert,
                            input wire [255:0] rx_ff_data_insert,
                            input wire [4:0] rx_ff_mod_insert,
                            input wire insert_empty,
                            input wire [7:0] des_node_id_insert,
                            input wire [2:0] pri_insert_i
                           );

//enum reg [3:0]{
//               IDLE,
//               INSERT,
//               NOT_INSERT              
//              } input_path_switch_cstate, input_path_switch_nstate;

parameter IDLE      = 3'b001;
parameter INSERT    = 3'b010;
parameter NOT_INSERT= 3'b100;

reg [2:0]    input_path_switch_cstate;
reg [2:0]    input_path_switch_nstate;

reg          rx_ff_dsav_mac_dl;


always @ (posedge clk or negedge rst_n)
  if(!rst_n)
    input_path_switch_cstate <= IDLE;
  else
    input_path_switch_cstate <= input_path_switch_nstate;

always @ ( * )
begin
  case(input_path_switch_cstate)
  IDLE: 
	if(rx_ff_dsav_mac)
		input_path_switch_nstate = NOT_INSERT;
	else if(insert_empty == 1'b0)
        input_path_switch_nstate = INSERT;
	else
	     input_path_switch_nstate = IDLE;

  INSERT:
    if(rx_ff_eop_insert)    
      input_path_switch_nstate = IDLE;
    else
      input_path_switch_nstate = INSERT;

  NOT_INSERT:
    if(rx_ff_eop_mac)
      input_path_switch_nstate = IDLE;
    else
      input_path_switch_nstate = NOT_INSERT;
  default:
    input_path_switch_nstate = IDLE;
  endcase
end


always@(*)
begin
	case(input_path_switch_cstate)
	IDLE:
		rx_rdy_mac = rx_rdy /*&& ~(rx_ff_dsav_mac == 1'b1 && rx_ff_dsav_mac_dl == 1'b0)*/;
	INSERT:
		rx_rdy_mac = 1'b0;
	NOT_INSERT:
  begin  
		rx_rdy_mac = rx_rdy;
  end
	default:
		rx_rdy_mac = rx_rdy;
	endcase
end

assign rx_rdy_insert = (input_path_switch_cstate == INSERT) ? rx_rdy : 1'b0;
assign rx_ff_sop     = (input_path_switch_cstate == INSERT) ? rx_ff_sop_insert:rx_ff_sop_mac;
assign rx_ff_eop     = (input_path_switch_cstate == INSERT) ? rx_ff_eop_insert:rx_ff_eop_mac;
assign rx_ff_dval    = (input_path_switch_cstate == INSERT) ? rx_ff_dval_insert:rx_ff_dval_mac;
assign rx_ff_dsav    = (input_path_switch_cstate == INSERT) ? rx_ff_dsav_insert:rx_ff_dsav_mac;
assign rx_ff_data    = (input_path_switch_cstate == INSERT) ? rx_ff_data_insert:rx_ff_data_mac;
assign rx_ff_mod     = (input_path_switch_cstate == INSERT) ? rx_ff_mod_insert:rx_ff_mod_mac;
//assign rx_ff_err     = (input_path_switch_cstate == INSERT) ? 1'b0:rx_ff_err_mac;
assign src_node_id_i= (input_path_switch_cstate == INSERT) ? 8'b0:src_node_id_i_mac;
// assign is_insert_frame = (input_path_switch_cstate == INSERT) ? is_insert_frame_insert:1'b0;
assign is_insert_frame    = (input_path_switch_cstate == INSERT) ? 1'b1:1'b0;
assign insert_des_node_id = (input_path_switch_cstate == INSERT) ? des_node_id_insert:10'd0;
assign pri_insert_o       = (input_path_switch_cstate == INSERT) ? pri_insert_i:3'd0;

//*****************test***************

// always @(posedge clk or negedge rst_n) begin
//   if (~rst_n) begin
//     // reset
//     rx_ff_dsav_mac_dl <= 1'b0;
//   end
//   else begin
//     rx_ff_dsav_mac_dl <= rx_ff_dsav_mac;
//   end
// end

endmodule
